1. Field of the Invention
The present invention relates to methods for verifying an integrated circuit prior to its manufacturing.
2. Discussion of the Related Art
The manufacturing of an integrated circuit is performed based on a set of masks. Each mask generally comprises a set of polygons which enable defining semiconductor areas, insulating areas, transistor gates, conductive tracks, and other elements of the integrated circuit. The set of masks corresponding to an integrated circuit is formed from a “physical” representation of the circuit on which are defined a set of polygons of various types from which it is possible to manufacture all the masks.
The polygons defined on a physical representation of an integrated circuit correspond to an assembly of interconnected components connected to input/output pads by electric connections. The components and the connections are generally explicitly defined in a “schematic” representation of the integrated circuit. Each component and each connection of the schematic representation corresponds to a set of polygons defined on the physical representation. Each set of polygons associated with a connection will be called a track hereafter.
FIG. 1 is an example of a schematic representation of an integrated circuit, and more specifically of a SRAM point corresponding to a basic element of a SRAM. The SRAM point comprises two looped inverters I1 and I2, the output of one inverter being connected to the input of the other one. The SRAM point further comprises two NMOS access transistors Ta1 and Ta2 controlled by a word line WL. Transistor Ta1 is placed between the output of inverter I1 and a bit line BL. Transistor Ta2 is placed between the output of inverter 12 and a bit line BLN.
FIG. 2 is a schematic representation of an inverter such as inverters I1 and I2. An inverter comprises a PMOS transistor P1 and an NMOS transistor N1 in series between a power supply Vdd and a ground GND. The gates of transistors P1 and N1 are connected to an input pad A. The drains of transistors P1 and N1 are connected to an output pad Z.
FIG. 3 is an example of a physical representation of a SRAM point corresponding to the above-described electric representation. This physical representation substantially corresponds to a top view of the integrated circuit masks such as it could be seen on a display screen and thus, what is at the top of the drawing is above what is at the bottom of the drawing. Similarly, what is described as being horizontal or vertical refers to an on-screen representation. Such considerations will be valid for all the physical representations described hereafter. Each transistor is represented by an active area and a gate area intersecting perpendicularly. Metal areas enable interconnecting active areas and/or gate areas.
Two rectangular active areas 1 and 2 are placed horizontally, area 1 being at the top and area 2 at the bottom of FIG. 3. Two rectangular active areas 3 and 4 are placed horizontally on each side of active area 2. Two gate areas 5 and 6 substantially having the shape of vertical tracks cut active areas 1 and 2 perpendicularly, areas 5 and 6 being respectively placed to the left and to the right. Two gate areas 7 and 8 substantially having the shape of short vertical tracks cut active areas 3 and 4. Active area 1 is P-type doped and active areas 2, 3, and 4 are N-type doped.
The portion of active area 1 located between gate areas 5 and 6 forms the source of the PMOS transistors of each of inverters I1 and I2. The portions of active area 1 located on either side of gate areas 5 and 6 form the drains of the PMOS transistors of inverters I1 and I2. Similarly, the portion of active area 2 located between gate areas 5 and 6 forms the source of the NMOS transistors of each of inverters I1 and I2. The portions of active area 2 located on either side of gate areas 5 and 6 form the drains of the NMOS transistors of inverters I1 and I2. The portions of active areas 3 and 4 located on either side of gate areas 7 and 8 form source/drain areas of access transistors Ta1 and Ta2.
Two rail-shaped horizontal metal areas 10 and 11 are respectively placed above and under active areas 1, 2, 3 and gate areas 5, 6, 7, and 8. Areas 10 and 11 are intended to be respectively connected to power supply Vdd and to ground GND. A metal area 12 connects track 10 (Vdd) to the portion of active area 1 forming the source of the PMOS transistors. A metal area 13 connects track 11 (GND) to the portion of active area 2 forming the source of the NMOS transistors. A metal area 14 connects the left-hand portions of active areas 1 and 2 corresponding to drain areas. Similarly, a metal area 15 connects the right-hand portions of active areas 1 and 2 corresponding to drain areas. Two metal areas 16 and 17 connect metal areas 14 and 15 respectively to gate areas 6 and 5. A metal area 18 connects the portions of active source/drain areas 2 and 3 located next to each other. Similarly, a metal area 19 connects the portions of active source/drain areas 2 and 4 located next to each other. The lateral portions of active areas 3 and 4 are respectively connected to two metal areas 20 and 21 corresponding to bit lines BL and BLN. Gate areas 7 and 8 are respectively connected to two metal areas 22 and 23 corresponding to word lines WL and WLN. Each connection between a metal area and an active area or a gate area is ensured by a conductive via represented by a cross placed in a square.
The existing methods for verifying an integrated circuit defined by a physical representation and a schematic representation such as described hereabove generally comprise the next three steps.
A first step consists of verifying the circuit functionality, this being generally performed by means of an electric simulation performed based on the schematic representation of the circuit. In an electric simulation, a series of states corresponding to a series of stimuli applied on the circuit inputs is defined based on an initial electric state of the circuit. For each state of the circuit, the electric voltage, or the logic level “0” or “1”, of each of the circuit connections, is defined. If necessary, especially in the case of so-called “analog” circuits, the value of the input or output currents of each of the circuit components is also determined. The analysis of the series of circuit states obtained after simulation enables verifying the circuit functionality.
A second step consists of verifying that the circuit such as defined by the physical representation fulfils all manufacturing constraints. This second step gathers several verifications known as DRC, DFM, and ERC (Design Rule Check, Design For Manufacturing, and Electrical Rule Check) and mainly consists of verifying the geometric features of each polygon (width, surface area, . . . ) and the intervals between the various polygons of the physical representation of the circuit.
A third step, known as the LVS step (Layout Versus Schematic), consists of verifying that all the polygons of the physical representation actually correspond to the components and connections of the schematic representation. For this purpose, a first list of components and of connections is “extracted” from the physical representation by performing a recognition of polygon groups, each corresponding either to a known component type, or to a connection. As an example, the association of a perpendicularly-intersecting active area and of gate area is recognized as defining a transistor. In parallel, a second list of components and of connections is established based on the schematic representation. It is then verified that the two lists do comprise the same components and identical connections between the various components.
Such existing integrated circuit verification methods do not enable detecting certain weaknesses of a circuit manufactured according to the most recent methods. The possibly weaknesses of a “modern” circuit are of various natures and each type of weakness generates a malfunction of the circuit in specific circuit use conditions. When the circuit is used in conditions likely to “reveal” certain weaknesses of the circuit, the most current phenomena that can occur at the circuit level are the following.
A known phenomenon is the electromigration of one or several metal areas which generally results in a cutting of the metal tracks. The potential track electromigration risks are all the greater as the size and the complexity of the circuits is greater. No circuit verification method enables detecting areas at risk. Only the designer's vigilance can avoid this type of problem.
Another known phenomenon is the modification of the voltage, in other words, a state switching, of a metal track due to a stray capacitive coupling between two metal tracks.
Another known phenomenon is the local supply voltage decrease, in portions of a circuit where many components simultaneously conduct strong electric currents, the voltage decrease being proportional to the total requested current and to the resistance of the supply tracks. This phenomenon is generally observed in so-called synchronous circuits for which the latch registers all switch at the same moment. A local decrease in the power supply results in a poor operation of the under-supplied cells.
Certain weak areas likely to cause the occurrence of the last two above-mentioned phenomena can be partially detected by performing an electric simulation of the circuit based on a “improved” schematic representation comprising parasitic components (resistors, capacitors, coils) determined from the physical representation of the circuit and especially from all the conductive areas corresponding to the various connections defined in the schematic representation. However, current methods for extracting all these parasitic components do not enable determining with a sufficient accuracy the resistive, capacitive, and inductive values of the parasitic components, and this, all the more as the circuit size is large and as the physical representation is organized in several hierarchical levels. Further, the size of the “improved” schematic representation obtained after extraction of the parasitic components is generally from two to three times as high as the schematic base representation and its electric simulation may be very long and require many computer resources. The simulation difficulty then results in limiting the number of tested stimuli, which strongly decreases the possibilities of detecting possible weaknesses. Further, even if wide hardware and time resources are available, the definition of “exhaustive” stimuli enabling testing all the cases of use often appears to be impossible.
The above-mentioned problems appear when a metal track has a shape or a positioning with respect to the other tracks which is inappropriate to its use. A problem may occur on a track, for example, in the case where the current density running through it is too high or in the case where the frequency of the electric signal running through it or running through a close track is too high.